1. Technical Field
The present invention relates to semiconductor memories. More particularly, the present invention relates to a temperature sensing circuit using a delay locked loop (DLL) and a temperature sensing method thereof, capable of reducing time and cost through an automatic compensation of sensed temperature.
2. Description
A temperature sensor is generally used in various industry fields relating to temperature. Particularly in a semiconductor memory field, it has been mainly used for a refresh operation of semiconductor memories.
In general, a DRAM (Dynamic Random Access Memory) is a unit memory device capable of writing data such that when storing data of ‘1’ in a memory cell, a high potential is applied to and held by the memory cell, thereby writing data. And when storing data of ‘0’, a low potential is applied to and held by the memory cell, thereby writing data.
A gathered charge should keep a constant level in the state so that a capacitor of the memory cell has an ideal state, and so that potential in a connection terminal of the capacitor is not changed. In actuality, in a characteristic aspect of a capacitor, the stored charge leaks as leakage current as time lapses. Thus it is difficult to check and confirm whether the written data is ‘1’ or ‘0’.
To constantly keep data, therefore, the memory device needs to periodically sense and amplify data stored in the memory cell. Also, it is necessarily required to re-store the data in the memory cell. Such serial procedures are called a refresh.
As temperature increases, a data maintenance time of the semiconductor memory cell is reduced. In other words, a data loss in the memory cell caused by an end of data maintenance time can be prevented by refreshing the semiconductor memory cell before the data maintenance time of the semiconductor memory is ended. A period of such refresh operation is decided so that the refresh operation is performed on the basis that the semiconductor memory cell has a relatively high temperature.
Unlike a relatively high temperature required for the refresh operation, in a general temperature, predetermined matching to a relatively high temperature is performed even though a data maintenance time is not completed. This may be ineffective because the refresh operation is performed in the semiconductor memory cell in the general temperature and so a general operation such as read/write cannot be implemented.
A solution to such problem may include using a temperature sensor to perform a refresh operation in a semiconductor memory cell. An internal temperature of the semiconductor memory device can be sensed through the temperature sensor, thereby controlling a refresh period according to the sensed temperature. However, this requires a relatively faster and more precise temperature sensing operation.
FIG. 1 illustrates a structure of temperature sensing circuit according to a conventional art. Referring to FIG. 1, a temperature sensing circuit includes a first delay 10, second delay 20 and D flip-flop 30.
In the first delay 10, an inverter, in which a voltage having a level higher than a reference power voltage is used as a power voltage level High VDD, is provided as a delay cell, and a plurality of the delay cells IVT10, IVT12 . . . IVTn-2, and IVTn, are connected in series. The first delay 10 receives an external clock ECLK from the outside, and generates a first delay pulse DP1, and transfers the pulse to the D flip-flop 30. The first delay pulse DP1 has a characteristic delay amount that increases according to a temperature increase.
The second delay 20 has a structure that includes a voltage having a level lower than the reference power voltage, the voltage being a power voltage level Low VDD. An inverter is provided as a delay cell, and a plurality of the delay cells IVT20, IVT22 . . . IVT2n-2, and IVT2n, are connected in series. The second delay 20 receives external clock ECLK from the outside, and generates a second delay pulse DP2, and transfers the pulse to the D flip-flop 30. The second delay pulse DP2 has a characteristic delay amount that decreases according to a temperature increase.
The D flip-flop 30 receives the first delay pulse DP1 as data, and receives the second delay pulse DP2 as a clock, then performs a corresponding operation. For example, a state of the first delay pulse DP1 provided at a rising edge of the second delay pulse DP2 is output as the data.
A general temperature sensing operation based on an internal temperature change of the semiconductor memory device is described as follows.
A determination temperature in the general temperature sensing circuit indicates temperature to be sensed within the semiconductor memory device. When internal temperature of the semiconductor memory device is lower than the determination temperature, the first delay 10 generates first delay pulse DP1 of a fast phase and outputs it to the D flip-flop 30. At this time, the second delay 20 generates second delay pulse DP2 having a relatively slow phase as compared with the first delay pulse DP1, and outputs it to the D flip-flop 30.
The D flip-flop 30 outputs a state of the first delay pulse DP1 provided at a rising edge time point of the second delay pulse DP2 as data. At this time, the first delay pulse DP1 has a phase faster than the second delay pulse DP2, thus the first delay pulse DP1 has a high level at the rising edge time point of the second delay pulse DP2 and so the D flip-flop 30 outputs data of a high level. Accordingly, it can be confirmed that internal temperature is lower than the determination temperature.
To the contrary, when internal temperature of the semiconductor memory device is higher than the determination temperature, the first delay 10 generates first delay pulse DP1 of a slow phase and outputs it to the D flip-flop 30. At this time, the second delay 20 generates second delay pulse DP2 having a relatively fast phase as compared with the first delay pulse DP1, and outputs it to the D flip-flop 30.
At this time, the first delay pulse DP1 has a phase slower than the second delay pulse DP2. Thus, the first delay pulse DP1 has a low level at the rising edge time point of the second delay pulse DP2, and so the D flip-flop 30 outputs data of a low level. Accordingly, internal temperature can be clarified to be higher than the determination temperature.
That is, when the internal temperature is lower than the determination temperature, a high level signal is output, and when the measured temperature is higher, a low level signal is output, thereby performing an operation corresponding to an internal temperature change of a semiconductor memory device.
However, it often occurs that an actually measured temperature may deviate from a determination temperature targeted in designing a temperature sensing circuit due to a process fluctuation and an error of model parameter and design etc. Therefore, a calibration (hereinafter, referred to as ‘compensation’) operation is required for a compensation of a temperature trip point. The compensation operation is performed by measuring a trip point of temperature through a normal test MRS (Mode Register Set), and by fusing it through laser. Specifically, the compensation operation is performed by adjusting a stage number of delay cells constituting the first or second delay 10 or 20, or by locking power source voltage VDD supplied to the first or second delay 10 or 20 through a control of a regulator.
However, in this case, it is inconvenient to have to find out one by one a trip point through the test MRS and fuse it as a determination temperature in order to perform the compensation operation. This requires much time and cost, particularly in a semiconductor memory field based on a characteristic of mass production.
Accordingly, some embodiments of the invention provide a temperature sensing circuit using a delay locked loop and a temperature sensing method thereof. A consumption of time and cost through the temperature compensation of a sensed temperature can be reduced, and a temperature compensation operation can be performed automatically. Additionally a precise temperature sensing operation can be obtained.
According to an embodiment of the invention, a temperature sensing circuit using a delay locked loop comprises a locked delay unit for receiving an external clock and generating a locked delay pulse keeping a constant delay amount regardless of temperature; a variable delay unit having a chain structure of a plurality of delay cells depending upon temperature, the variable delay unit being for receiving the external clock and generating a plurality of variable delay pulses having respectively different delay amounts based on temperature; and a decision control unit for sensing a determination temperature by using a phase difference between one selected from the variable delay pulses and the locked delay pulse.
The locked delay unit may comprise one delay cell having a structure of at least one inverter. A delay cell of the variable delay unit may be an inverter. The decision control unit may comprise a D flip-flop for receiving the locked delay pulse as a reference clock and receiving the one selected variable delay pulse as data, and outputting a corresponding delay pulse to the outside. The temperature sensing circuit may further comprise at least one delay locking unit for selecting a variable delay pulse that synchronizes to the locked delay pulse at a predetermined temperature, from the variable delay pulses, and locking the selected pulse.
The delay locking unit may comprise a phase sensor and a multiplexer. The phase sensor repetitively performs an operation of comparing a phase of one of the variable delay pulses with a phase of the locked delay pulse, and generating its corresponding comparison signal, until the delay is locked. The multiplexer repetitively performs an operation of selecting one variable delay pulse corresponding to the comparison signal of the phase sensor, from the variable delay pulses, and outputting the selected pulse to the phase sensor, until the delay is locked.
The delay locking unit may further comprise a counter for generating a count signal to provide as a selection reference of variable delay pulse in the multiplexer in response to the comparison signal output from the phase sensor. The delay locking unit may further comprise a fusing unit for performing a fusing operation so that a variable delay pulse selected in locking a delay amount in the delay locking unit is locked and output to the decision control unit through the multiplexer. When the number of temperatures to be sensed is plural, the delay locking units may be further adapted corresponding to the number of sensing temperatures.
According to another embodiment of the invention, a temperature sensing compensation circuit using a delay locked loop comprises a locked delay unit for generating a locked delay pulse having a constant delay regardless of temperature, a variable delay unit having a chain structure of a plurality of delay cells depending upon temperature, the variable delay unit being for receiving an external clock and generating a plurality of variable delay pulses having different delay amounts based on temperature, and a delay locking unit for repetitively performing an operation of selecting one variable delay pulse that synchronizes to the locked delay pulse at a predetermined temperature, from the variable delay pulses, until the delay is locked. The temperature sensing compensation circuit may further comprise a fusing unit for performing a fusing operation so that the selected variable delay pulse is locked and output, in locking the delay amount of the delay locking unit. When the number of determination temperatures to be sensed is plural, the delay locking unit may be adapted corresponding to the plural number thereof.
According to another embodiment of the invention, an operating method of a temperature sensing circuit using a delay locked loop comprises a first step of receiving an external clock input from the outside and generating a locked delay pulse having a locked delay amount regardless of temperature, and receiving the external clock and generating a plurality of variable delay pulses having different delay amounts according to a temperature change; and a second step of sensing a determination temperature by using a phase difference between one selected from the variable delay pulses and the locked delay pulse. The method may further comprise, before the second step, selecting a variable delay pulse synchronizing to the locked delay pulse from the plurality of variable delay pulses and locking it at the determination temperature, and compensating the sensed temperature.
According to another embodiment of the invention, a temperature sensing compensation method using a delay locked loop comprises a first step of receiving an external clock input from the outside and generating a locked delay pulse having a locked delay amount regardless of temperature, and receiving the external clock and generating a plurality of variable delay pulses having different delay amounts according to temperature; a second step of selecting one of the plurality of variable delay pulses and then comparing a phase of the one selected variable delay pulse with a phase of the locked delay pulse, and deciding whether the phases are identical; and a third step of locking the selected variable delay pulse when the phases of the selected variable delay pulse and the locked delay pulse are identical, and repetitively performing the second step until the phases become identical, when the phases are not identical.
In the second step it can be decided whether the phases are identical through a generation of up/down signal as a phase comparison signal between the locked delay pulse and the selected variable delay pulse. The third step may further comprise, when phases between the selected variable delay pulse and the locked delay pulse are identical, performing a fusing operation so that the selected variable delay pulse is locked and output, or when not identical, generating a count signal to reselect a variable delay pulse. The method may further comprise a fourth step of repetitively performing the first to third steps at each determination temperature when the number of determination temperatures is plural.
According to another embodiment of the invention, a temperature sensing circuit using a delay locked loop comprises a locked delay unit for generating a locked delay pulse having a constant delay regardless of a temperature change; a variable delay unit for generating a plurality of variable delay pulses having different delay amount that is changed depending upon the temperature change; a plurality of delay locking units for performing independently every plural determination temperatures, an operation of selecting a variable delay pulse synchronizing to the locked delay pulse from the plurality of variable delay pulses generated under a determination temperature state, and locking it, in a compensation operating mode, and for outputting variable delay pulses locked corresponding to each of the plurality of determination temperatures in a sensing temperature state in a temperature sensing mode; and at least one decision control unit for comparing a phase of at least one of the variable delay pulses output from the delay locking units with a phase of the locked delay pulse, and outputting at least one temperature signal.
The delay locking units may be provided corresponding to the number of sensing temperatures or the number of determination temperatures. Each of the delay locking units may comprise a multiplexer, phase sensor, counter and fusing unit. One decision control unit is adapted in the temperature sensing circuit. The temperature sensing circuit may further comprise a multiplexer for selecting one delay locking unit corresponding to a determination temperature from the plurality of delay locking units, and providing variable delay pulse to the decision control unit. The temperature sensing circuit may comprise a plurality of decision control units that are adapted corresponding to the number of the delay locking units and that individually corresponds thereto. The plurality of decision control units may simultaneously compare the respective variable delay pulses provided from the respective delay locking units, with the locked delay pulse, and output a plurality of temperature signals.
According to another embodiment of the invention, a temperature sensing method using a delay locked loop comprises starting a compensation operating mode; generating a locked delay pulse having a locked delay amount regardless of temperature under a specific determination temperature, and a plurality of variable delay pulses having a delay amount changed according to a temperature change; performing independently every plural determination temperatures, an operation of selecting a variable delay pulse synchronizing to the locked delay pulse from the plurality of variable delay pulses, and locking it; starting a temperature sensing mode; and comparing a phase of variable delay pulse locked corresponding to a determination temperature selected from the plurality of determination temperatures, with a phase of the locked delay pulse, and sensing a temperature, in a sensing temperature state.
Accordingly, a consumption of time and cost required for a temperature compensation can be reduced, and further, an automatic temperature compensation and a precise temperature sensing operation can be obtained.